The present invention relates to a semiconductor integrated circuit and, more particularly, to a signal output circuit having a shutdown function of switching between the shutdown disable state and shutdown enable state of an output signal in accordance with a single-phase digital signal.
A signal output circuit using an impedance conversion circuit such as a transistor differential pair or emitter follower is used as the output stage of a TIA (TransImpedance Amplifier), LA (Limiting Amplifier) which amplifies a light signal, or the like or the driving circuit of an LD (Laser Diode).
In many cases, an impedance conversion circuit such as a transistor differential pair or emitter follower used as such a signal output circuit includes, on the emitter terminal side of an output transistor, a current source transistor which supplies an operating current to the output transistor. For this reason, shutting down the supply of a current to the output transistor by setting the base voltage of the current source transistor to a threshold or less can shut down signal output from the output transistor.
Conventionally, Japanese Patent Laid-Open No. 2007-158084 has disclosed an LD driver circuit using NMOSs as a signal output circuit having a shutdown function of shutting down such signal output. FIG. 8 shows a conventional signal output circuit.
In this signal output circuit, at the shutdown disable time, a transistor differential pair constituted by npn transistors Q1 and Q2 (output transistors) amplify differential signals input to terminals ISN and ISP to a degree sufficient to drive an LD, and the amplified signals are output from terminals OSP and OSN.
An npn transistor Q3 and a resistor RSS are respectively a constant current source transistor and its constant current source stabilizing resistor. These two elements constitute a current source for supplying operating currents for performing shutdown disable operation with respect to the differential pair Q1 and Q2.
In addition, an N-type MOS transistor MN1 connected between the base terminal of the transistor Q3 and a terminal VCS and an N-type MOS transistor MN2 connected between the base terminal of the transistor Q3 and a power supply potential VEE are switches which selectively switch one of VCS and VEE as a voltage to be applied to the base terminal of the transistor Q3.
At the shutdown disable time, differential signals ISHN and ISHP input to the gate terminals of the MOS transistors MN2 and MN1 are respectively set at low level and high level to turn off the MOS transistor MN2 and turn on the MOS transistor MN1. With this operation, the voltage VCS is applied to the base terminal of the transistor Q3 to supply operating currents for performing shutdown disable operation from the transistor Q3 to the differential pair Q1 and Q2. As a result, the differential input signals input to the terminals ISN and ISP are output from terminals OSP and OSN via the differential pair Q1 and Q2.
In contrast, at the shutdown enable time, the differential signals ISHN and ISHP are respectively set at high level and low level to turn on the MOS transistor MN2 and turn off the MOS transistor MN1. With this operation, since the power supply potential VEE is applied to the base terminal of the transistor Q3, no operating currents are supplied from the transistor Q3 to the differential pair Q1 and Q2. As a result, the differential input signals input to the terminals ISN and ISP are not output from the differential pair Q1 and Q2, thereby setting a shutdown enable state.
According to this conventional technique, it is necessary to use NMOS transistors for switching between the shutdown disable state and shutdown enable state in addition to npn transistors. For this reason, manufacturing requires not only a manufacturing process for npn transistors, e.g., a general InP HET process, but also a manufacturing process for NMOS transistors. This complicates the manufacturing process and makes impossible to form a signal output circuit using a compound semiconductor substrate on which npn transistors and NMOS transistors are difficult to form together.
In addition, the above conventional technique requires the differential signals ISHN and ISPN as digital signals for externally switching between the shutdown disable state and shutdown enable state, and cannot switch between the shutdown disable state and shutdown enable state by using single-phase digital signals. For this reason, this technique cannot be directly applied to any circuit to which single-phase digital signals are output as signals for switching between the shutdown disable state and shutdown enable state. This limits the application range of a signal output circuit itself.